Figure 1

The Internet Streaming SIMD Extensions consist of 70 instructions and includes single instruction, multiple data for floating-point, additional SIMD-integer and Cacheability control instructions. Some of the benefits to desktop and Internet applications of Internet Streaming SIMD Extensions include:

• Higher resolution and quality images can be viewed and manipulated than previously possible.
• High quality audio, MPEG2 video, and simultaneous MPEG2 encoding and decoding.
• Reduced CPU utilization for speech recognition, as well as higher accuracy and faster response times.

Multiple Branch Prediction: Predicts program execution through several branches, accelerating the flow of work to the processor.
Dataflow Analysis: Creates an optimized, reordered schedule of instructions by analyzing data dependencies between instructions.
Speculative Execution: Carries out instructions speculatively and based on this optimized schedule, ensures that the processor�s superscalar execution units remain busy, boosting overall performance.

Intel MMX technology includes new instructions and data types that allow applications to achieve a new level of performance. Intel�s MMX� technology is designed as a set of basic, general-purpose integer instructions that are easily applied to the needs of a wide diversity of multimedia and communications applications.

The highlights of the technology are:

• Single Instruction, Multiple Data (SIMD) technique
• 57 new instructions
• Eight 64-bit wide MMX� technology registers
• Four new data types

The Intel® Celeron® processor includes two separate 16 KB level 1 (L1) caches, one for instruction and one for data. The L1 cache provides fast access to the recently used data, increasing the overall performance of the system.

The Advanced Transfer Cache (ATC) consists of microarchitectural improvements to provide a higher data bandwidth interface between the level 2 cache and the processor core that is completely scaleable with the processor core frequency.

Features of the ATC include:

• Non-Blocking, full speed, on-die level 2 cache
• Reduced latency interface to cache data (as compared to discrete caches)

A Discrete, off-die level 2 (L2) cache. This L2 cache consists of a unified, non-blocking cache that improves performance over cache-on-motherboard solutions by reducing the average memory access time and by providing fast access to recently used instructions and data. Performance is also enhanced over cache-on-motherboard implementations through a dedicated 64-bit cache bus.

• Intel® Celeron® processors are available in the Flip-Chip Pin Grid Array (FC-PGA), and the Flip-Chip Pin Grid Array 2 (FC-PGA2) package (with an Integrated Heat Spreader). (see Figure 1 above)
• Incorporates separate 16 Kbyte level-one caches (32 Kbyte total), one for instructions and one for data.
• Incorporates two separate 16 KB, Level 2 Advanced Transfer Cache, Non-blocking, full speed, on-die level-two cache with reduced latency interface to cache data (as compared to discrete caches).
• A pipelined Floating-Point Unit (FPU) for supporting the 32-bit and 64-bit formats specified in IEEE standard 754, as well as an 80-bit format.
• Parity-protected address/request and response system bus signals with a retry mechanism for high data integrity and reliability.

• Built-in Self Test (BIST), provides single stuck-at fault coverage of the microcode and large PLAs, as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLBs) and ROMs.
• IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture mechanism, allows testing of the Intel® Celeron® processor through a standard interface.
• Internal performance counters can be used for performance monitoring and event counting.

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