General Description
The PDCharm2.0 and PDCharm2.5 single-chip baseband solutions for PDC, were designed and developed by DSPC, an Intel company. They provide a compact single-chip solution for dual rate (full and half rate) baseband processing for Personal Digital Cellular (PDC) handheld phones, as specified by the RCR STD-27H standard. The PDCharm2.X single chip offers very low power consumption and simple interfacing with audio and RF sections. Based on advanced Digital Signal Processing (DSP) techniques, it provides a cost-effective solution that can be easily adapted to new system requirements and services.

The importance of these new products is their strong data-related capabilities that enable and greatly support resource-consuming data applications, the significant new enhancements include: high-speed operation of the micro-controller, large size internal RAM and simplified DMA controller. With all of the above it efficiently supports applications such as JAVA* and others. In particular PDCharm2.X supports i-Mode* and Packet Data through logic circuits and DSP software.

A unique feature of the PDCharm series is its capability to support the requirements and the services of all PDC carriers in the same chip. That includes, among other features, the enabling of i-Mode* operation and of packet data services, such as the Half Duplex Packet (HDP) in PDCharm2.0 and Full Duplex Packet (FDP) in PDCharm2.5 and all the different vocoders used by various carriers. Both RF bands 800MHz and 1500MHz are supported by the PDCharm series, while PDCharm2.X also supports dual band handsets. The PDCharm2.X is only available in Japan, for the PDC market.

Figure 1 presents a general block diagram for the new chip.

Figure 1: System Block Diagram of the PDCharm2.X

PDCharm2.X has a small BGA package, has extremely low power consumption and does not require any tuning over the entire operating temperature range, thus simplifying manufacturing. PDCharm2.X is a mixed signal ASIC, built around a powerful DSP and an ARM7TDMI* RISC CPU with all required peripherals, logic and analogue cells integrated into a single chip. It supports new data applications by the high capabilities of the micro-controller. A small internal ROM provides a boot loader program. The main host program should reside on an external Flash memory, but a large internal RAM allows for the download of routines from the external memory for faster execution and for lower power consumption. PDCharm2.X also integrates a Real Time Clock (RTC) module with a low power 32KHz oscillator.

At the audio front end, PDCharm connects directly to every popular PCM audio codec device via the commonly used serial data interface. PDCharm2.X introduces a new audio feature - AVC, which enhances the intelligibility of the received voice under noisy conditions. Another function is speaker dependent voice recognition, featuring best-known and excellent performance of recognition rate in noisy mobile environment, compared with the performance known in the cellular market so far. It further allows a large number of names - up to 64 voice entries. Like the previous devices in the PDCharm series, PDCharm2.X performs VSELP, ACELP, CS-ACELP or PSI CELP speech coding/decoding (selected by a host command); performs noise suppressions, echo cancellation and supports a voice memo function.

The RF/IF interface includes a transmit path and a receive path with antenna diversity control. PDCharm connects to a balanced IQ modulator on the transmitter path (through very simple circuitry) and directly to an IF limiter-amplifier device on the receiver path. A PLL control via SPI can interface with popular RF PLL ICs. PDCharm implements the entire baseband modem functions - channel coding, DQPSK modem, frequency & time acquisition and tracking, TDMA burst control and diversity handling. PDCharm contains all the analogue control circuitry required for the handset. In addition to measuring the RSSI signal, all other analogue monitoring and control capabilities are performed by the chip. PDCharm also provides programmable timing signals that perform both TDMA control and power-saving functions for the entire RF/IF subsystem. The flexible programmable timing is set through simple Host commands.

Figure 2: System Block Diagram of a typical handset design using PDCharm2.X

Features

• VSELP, ACELP, CS-ACELP (full rate) and PSI-CELP (half rate) speech coders/decoders
• Low rate speech coder for Voice Memo Pad (7.5Kbps)
• Enhanced Noise Suppressor (ENS) for TX and RX paths
• Hands-free Echo Cancellation for normal Handset operation, speaker-phone and car adaptor applications
• Audio Automatic Volume Control (AVC)at the receiver for noisy mobile environment
• Speaker dependent Voice Recognition for name dialing
• RSSI measurements, antenna diversity control
• Full PLL synthesizer control with minimal MCU load
• Time and frequency synchronization/tracking
• ECC, scrambling
• Compensates for group delays introduced by RF, IF, and baseband circuits
• Measurement of battery, HPA and temperature by auxiliary inputs to a 10-bit ADC
• Built in low current and low cost Digital to Analog converters
• Extensive testability functions and calibration assist
• External data interface for:
  • Direct connection to data and fax adapters
  • Bit error rate testing
• Support for the physical layer requirements of:
  • One Slot Packet Data and 3-Slot Packet Data
  • Half Duplex Packet (HDP) by PDCharm2.0 and Full Duplex Packet (FDP) by PDCharm2.5
  • LAPB for the external data I/F
  • ARQ function for TCH data communication
• Low power consumption in waiting mode

Features - ARM MCU Section

• ARM7TDMI* operates at programmable frequencies (by PLL) up to 40MHz in PDCharm2.0 and 56Mhz in PDCharm2.5
• Internal ROM for Boot Loader and large internal RAM
• Interface to Page Mode Flash in PDCharm2.5
• UARTs and SPIs
• 16 general purpose Timers + Watch Dog Timer
• Keypad I/F plus numerous GPIO pins
• Bus control (simplified DMA) for external memories
• Internal interrupt controller
• Power management
• JTAG and Extended Trace Module (ETM)
• Monitor and debug capabilities
• 23 lines of MCU address bus (to support up to 8Mbyte Flash memory)
• 32 KHz Oscillator Circuit and Real Time Clock (RTC) module

Operating Conditions

• Analog I/O Levels : 0 to VDD, user-programmable offset and gain
• Power supply (Vdd) : 2.5 to 3.0V for analog/digital IO, 1.65V to 1.95V for core logic systems
• Typical current consumption @ nominal supply, the ARM executing at 7.2MHz from internal RAM:
  Conversation Mode 16mA (full rate), 19mA (half rate)
  Waiting Mode 150�A (average) assuming 1 PCH slot
• Operating Temperature range -20� to 85�C

Packaging Data