• Processor Highlights
• Intel® NetBurst" Microarchitecture
• Hyper-Threading Technology
• 400 MHz System Bus
• Level 1 Execution Trace Cache
• Level 2 Advanced Transfer Cache (256 KB)
• Integrated Level 3 Cache (1 MB or 512 KB)
• Higher Core Frequencies
• Rapid Execution Engine
• Advanced Dynamic Execution
• Enhanced Floating-point and Multi-media Unit
• Streaming SIMD Extensions 2 (SSE2)
• Manageability Features
• Features Used for Testing and Performance Monitoring
• Product Performance
• Related Information

Intel® NetBurst" microarchitecture
The Intel NetBurst Microarchitecture is binary compatible with previous generation Intel Architecture (IA-32) processors. It adds new features beginning with innovative techniques that enhance processor execution such as Higher Core Frequencies, a Rapid Execution Engine, and Advanced Dynamic Execution. The pipeline depth in the processor is doubled, allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in one half of the internal core clock cycle. The Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor.

Hyper-Threading Technology
Going beyond GHz, Intel is changing the landscape of processor design and performance by supporting multiple software threads on each processor in the system. Hyper-Threading Technology is a groundbreaking technology that will enable new capabilities and applications for the evolving internet and enterprise infrastructure. Hyper-Threading Technology allows your multi-threaded server applications to execute more than one thread per physical processor, increasing the throughput of your server applications and enabling you to scale with processor requirements to handle future workloads. This technology provides tangible benefits for today's server applications by:

400 MHz System Bus
The 400 MHz system bus is a quad-pumped bus running off of a 100 MHz system bus clock, making 3.2 Gigabytes per second (3,200 Megabytes per second) data transfer rates possible. This can be up to 4X the system bus bandwidth provided by the Intel® Pentium® III Xeon" processor providing much greater throughput for multiple processors accessing memory and I/O.

Level 1 Execution Trace Cache
In addition to the 8 KB Level 1 Data cache, the Intel® Xeon" processor MP includes an Execution Trace Cache that stores up to 12K of decoded micro-ops instructions in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored. The result is a means to deliver a high volume of instructions to the processor's execution units and a reduction in the overall time required to recover from branches that have been mis-predicted.

Level 2 Advanced Transfer Cache (256 KB)
The 256 KB L2 Advanced Transfer Cache (ATC) delivers a much higher data throughput channel between the Level 2 Cache and the processor core. The Advanced Transfer Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, the Intel Xeon processor MP can deliver a data transfer rate of core speed multiplied by 32 bytes, reported in GBs which is nearly 2X the transfer rate of the Intel PentiumIII Xeon processor's L2 cache. This contributes to the Intel Xeon processor MP's ability to keep the high-frequency execution units executing instructions vs. sitting idle.

Integrated Level 3 Cache (1 MB or 512 KB)
The Intel Xeon processor MP introduces an additional third level of cache, located on the processor die, designed specifically to meet the compute needs of enterprise server applications. The Integrated Level 3 Cache is available in 1 MB or 512 KB options and is coupled with the 400 MHz system bus to provide a high bandwidth path to memory. The efficient design of the Integrated Level 3 cache provides a faster path to large data sets stored in cache on the processor. This results in reduced average memory latency and increased throughput for larger server workloads.

Higher Core Frequencies
Higher core frequencies are capable through the Intel NetBurst microarchitecture which doubles the pipeline depth compared to the P6 microarchitecture used on today's Intel Pentium III Xeon processors. One of the key pipelines, the branch prediction / recovery pipeline, is implemented in 20 stages in the Intel NetBurst microarchitecture, compared to 10 stages in the P6 microarchitecture. This technology significantly increases the performance, frequency, and scalability of the processor.

Rapid Execution Engine
Two Arithmetic Logic Units (ALUs) on the Intel Xeon processor MP are clocked at twice the core processor frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in � a clock cycle. For example, the Rapid Execution Engine on a 1.60 GHz Intel Xeon processor MP runs at 3.20 GHz.

Advanced Dynamic Execution
The Advance Dynamic Execution engine is a very deep, out-of-order speculative execution engine that keeps the execution units executing instructions. The Intel Xeon processor MP can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch mis-predictions by about 33% over the P6 generation processor's branch prediction capability. It does this by implementing a 4 KB branch target buffer that stores more detail on the history of past branches, as well as by implementing a more advanced branch prediction algorithm.

Enhanced Floating-point and Multi-media Unit
The Intel Xeon processor MP expands the floating-point registers to a full 128-bit and adds an additional register for data movement which improves performance on both floating-point and multi-media applications.

Streaming SIMD Extensions 2 (SSE2)
With the introduction of SSE2, the Intel NetBurst microarchitecture now extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They can accelerate a broad range of applications including video, speech, and image; photo processing; encryption; financial; engineering and scientific applications.

Manageability Features
Thermal sensors on the Intel Xeon processor MP enable the system to actively monitor and manage thermal conditions and reduce the chance of system failure. This processor also includes Error Correction Code (ECC) on the Integrated Three-Level cache architecture to maintain the integrity of mission-critical data. The Intel Xeon processor MP also comes with a System Manageability Bus (SMBus) which enables efficient communications between components and allows for easy access to system manageability information stored in the Processor Information ROM. These features of the Intel Xeon processor MP provide platform-level manageability for reliable, robust server operation and ease of management.

Features Used for Testing and Performance Monitoring
IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Intel Xeon processor MP and system connections through a standard interface.

Product Performance
The Intel Xeon processor MP (available in 1 MB or 512 KB Integrated Level 3 cache versions) delivers the next generation of performance for e-Business and enterprise server applications. Processor performance data is available on the Intel® Xeon" Processor MP Server Performance website.

Related Information

The Intel Xeon processor MP erratum is available at Intel® Xeon" Processor MP Specification Update.