If Moore's Law holds true the doubling of transistors on a chip every couple of years chip features must shrink at an equivalently exponential rate. The narrower and circuit patterns and features, the faster electricity can move across a chip, boosting its performance. Infinitesimally small circuit patterns make it possible to fit more transistors on a chip, thereby increasing functionality and performance.

The process used to create circuit patterns is known as photolithography. Essentially, it uses light to create patterns on silicon. Layers of material are added and removed, resulting in progressively more complex circuits. The challenge is creating increasingly smaller feature sizes.

Intel is confident that the answer is Extreme Ultraviolet (EUV) lithography, which uses a series of mirrors to direct light with a wavelength of 13.5 nanometers (nm) to print exceptionally small features below 45 nm. This wavelength is almost 20 times shorter than current lithography technology. Precision mirrors are used because unlike lenses, they reflect rather than absorb EUV light.

Able to keep pace with Moore's Law, EUV lithography can potentially produce processors with speeds in excess of 10 GHz and memory chips with storage capacities that greatly exceed those of today.

Intel is spearheading the commercialization of EUV lithography, having ordered the industry's first EUV lithography beta tool from ASML, a manufacturer of advanced technology systems for the semiconductor industry.

Intel began funding EUV research in 1996 when it became evident that current chip-printing technologies were reaching their physical limits. A year later, Intel took a leadership position by forming a consortium, known as EUV Limited Liability Corporation (LLC). Today there are a total of six semiconductor companies funding research and construction of a prototype machine.

The alpha or prototype machine, called the Engineering Test Stand (ETS) is the result of collaboration between industry and government. It was funded by the EUV LLC and jointly built by Lawrence Berkeley National Laboratory, Lawrence Livermore National Laboratory and Sandia National Laboratories. Completed in April 2001, ETS is housed at Sandia in Livermore, CA and is used for testing and refining the technology. The commercial versions of the machine are being built by ASML.

The EUV beta tool, which is scheduled for delivery in 2005, will be used on 300 mm wafers to create components using Intel's 45 nm process technology. Today's state-of-the-art process technology measures 130 nm. A gamma, or production, version of the machine is expected to be available in 2007.

Learn more about how Intel is expanding Moore's Law.