Dr. Paolo Gargini is a Technology Strategist and Director of the Strategic Research Group for Intel Corporation, Santa Clara. He has also been distinguished as an Intel Fellow.
Since joining Intel in 1978, Dr. Gargini has conducted studies on contact electromigration and failure mechanisms of advanced MOS structures in the area of Process Reliability. He has also been responsible for developing the building blocks of HMOS III and CHMOS III technologies used in the 1980s, and coordinating the development of the modules common to memory and logic technologies.
He has done research at LAMEL in Bologna, Stanford Electronics Laboratory, and Fairchild Camera and Instrument Research and Development. Dr. Gargini has authored a number of papers on CMOS, CCD, and thin film technologies, and holds patents on EPROM and interconnection technologies. In addition, Dr. Gargini has been a keynote speaker at numerous conferences and universities throughout the United States and Europe.
Dr. Gargini received a doctorate in Electrical Engineering in 1970 and a doctorate in Physics in 1975 from the Universita di Bologna, Italy.