Focus:

Provide compiler technologies and work closely with Architecture/Circuit Labs to drive IA-64 micro-architecture research and enhance Intel's leadership in processors and platforms.

Be the driving force to advance and innovate static and dynamic compilation technology to provide IA-64 the leadership performance, throughput and reliability.

Be the corporate research team to identify, develop and prototype the leading-edge enabling technology for emerging system software domains like new languages to make IA be the best for them or create new business opportunity for Intel.

Key Contacts: Staff

Publications

Projects:

The Gluon Project

People: Li-Ling Chen, Roy Ju, Shih-wei Liao, Tin-fook Ngai, Mauricio Serrano, Youfeng Wu

Purpose:
GLUON is an IA-64 research compiler with a flexible infrastructure and a set of powerful supporting components allowing researchers to quickly prototype new compiler technologies for existing and future architectures. We work closely with Architecture/Circuit Labs to drive IA-64 micro-architecture research and enhance Intel's leadership in processors and platforms.

Our compiler incorporates state-of-the-art IA-64 code optimization and generation technologies, a flexible machine model, a set of powerful edge/path/data/value profilers and annotation tools.

Description:
We currently focus on two research projects:

1. Speculative multithreading
2. Memory optimizations

Speculative Multithreading
The Speculative Multithreading Project investigates the new concept of speculative multithread execution and develops the corresponding compiler technologies. It studies the behavior of speculative multithreaded programs, assesses their performance potentials and develops new program analysis, code generation and optimization algorithms. The existing Gluon compiler is being enhanced with the compilation model and supports for speculative multithread execution.

Memory Optimizations
The Memory Optimization Project focuses on memory sub-system of IA64 and develops the corresponding optimization technologies. It studies memory-intensive benchmarks, analyzes the memory behavior of programs, and develops compiler transformations or new micro-architecture features to improve the performance of memory sub-systems. The GLUON compiler is used to prototype emerging techniques for improving reference localities and hiding load latencies.

Related links: Publications

People: Weldon Washburn, Rick Hudson, Michal Cierniak, Sreenivas Subramoney, Ken Lueh, Ali Adl-tabatabai, Tatiana Shpeisman

Purpose:
The Open Source Dynamic Computing Research Platform is a platform for bytecode system research. To date, an open source research platform that allows interchangeable modules implementing Just-In-Time (JIT) compilers and Garbage Collection (GC) has not been available to the academic research community. ORP (Open Runtime Platform) is an open source research infrastructure project that provides these features, thus enabling the rapid evolution of systems research in dynamic compilation and memory management.

Description:
ORP implements advanced JIT and GC interfaces. These interfaces allow the JIT, GC and remaining runtime systems to be developed in complete isolation and at independent rates. A major benefit is that JIT and GC researchers are relieved of the intractable task of developing a full system before they can innovate in their area of expertise. Initially ORP interoperates with GNU Classpath. GNU Classpath is an open source library for the Java* language. Current ORP source code compiles and runs on IA32 Linux and IA32 Windows 2000 operating systems. Future updates will include JIT and GC for IA64. GNU Make makefiles are included for Linux builds. Microsoft VC++ 5.0 project files are included for the Windows 2000 build.

Application Performance
The basic system incorporates a fast code generating JIT, as well as an optimizing JIT. It also includes several GC algorithms, ranging from a simple mark-sweep algorithm to an advanced train algorithm.

MRL academic papers on these topics are listed at Publications.

Related Links
Publications
Open Runtime Platform

People: Dong-Yuan Chen

Purpose:
We are building a dynamic optimization infrastructure on the Intel Itanium� processor. The infrastructure utilizes the hardware performance monitor in the Itanium processor to closely monitor the run-time execution behavior of an application. Hot spots or problematic regions are identified as candidates for run-time optimizations in a software-based dynamic optimizer. Optimizations are performed by the software-based dynamic optimizer and are applied on-the-fly to the application's binary image in memory to improve the overall performance of the application.

The infrastructure is intended to serve as a vehicle for researching hardware-assisted dynamic optimization paradigms. Here are some areas of research that we are interested in:

• Dynamic behavior of real-world applications
• Light-weight optimizations or scheduling algorithms
• Dynamic optimization system issues
• Hardware monitoring support to enable dynamic optimization
• Architecture or microarchitecture support for dynamic optimization systems

Related Links
Publications

People: Sun Chan. Buqi Cheng, Roy Ju, Qingyu Zhao

Purpose:
The Open Research Compiler (ORC) is an Itanium� Processor Family (IPF) (IA-64) open source research compiler available to research and open source communities for conducting compiler and architecture research. It is offered as part of Intel's initiative to lead research on instruction-level parallelism, thread-level parallelism and beyond. ORC incorporates advanced program analysis and optimization techniques, including sophisticated uses of IPF architectural features. It provides a robust, flexible research compiler with competitive performance to enable researchers to explore and investigate advanced research problems.

ORC allows research groups around the world to focus on studying advanced research issues without substantial up-front costs to build a compiler infrastructure. The compiler research efforts at the Microprocessor Research Labs (MRL) to study advanced compilation and architectural features on Intel Architectures are based on ORC. Intel continues to lead in microprocessors and high-performance computing.

Description:
The ORC is under active development and is scheduled for the first release by the end of 2001. To leverage well-developed technology, ORC is built upon an existing open source compiler, Pro64. The first release focuses on the development of advanced optimizations to effectively exploit IPF features, such as predication, speculation, and explicit parallelism. It also provides the research infrastructure support to explore different design choices of compilers and hardware, such as controlling optimization scope using program regions, parameterizing machine descriptions, and supporting various types of profiling feedback. Additional work has already been planned beyond the first release, to include further exploitation of IPF features and revamp key parts of machine-independent optimizations to achieve competitive execution performance. A number of important research problems have been targeted on ORC, such as the compiler and architectural support for various forms of multi-threading. Effective optimizations on memory hierarchy are also an important research topic.

We would like to invite researchers around the world to collaborate on ORC-based emerging research issues, such as integrated static and dynamic compilation frameworks, software-driven power management, compilation for specific domains of applications, code size, program analysis and performance tools, etc.

Related Links
Publications