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Strategic CAD Labs Strategic CAD Labs

Strategic CAD Labs (SCL) is one of Intel's main CAD research groups for silicon design technology. The team focuses their research on design technologies that will be needed 3+ years from now by the designers of Intel's next generation microprocessors.

SCL currently conducts research in three main areas:

Logic Verification
The SCL Logic Team conducts research in the following areas:

Formal methods for hardware verification

Advanced dynamic validation technologies

PV & Design Research
The Performance Verification & Design Team conducts research the following areas:

Large scale interconnect modeling

Multi-GHz design and performance verification

Synthesis Research
The High Level Design & Synthesis Team researches technologies for:

High level design and synthesis

Rapid design construction


There are opportunities for funding research including direct department funding as well as the Design Science Technical Committee (DSTC) which supports research work focused in the design science areas. SCL funds academic research in relevant areas of interest as well. Descriptions of currently funded research and information on how to submit funding proposals can be found at funding. Intel also participates in consortiums which fund design science based research including the Semiconductor Research Corporation (SRC)*, as well as different focus centers under the Microelectronics Advanced Research Corporation (MARCO)*, For more information on these funding opportunities, you may send inquiries to


Looking for the right opportunity to conduct state-of-the-art applied research on real design problems? Internships are available in a variety of departments within Design Technology. SRC funded students are encouraged to seek out interships at Intel as well. SCL offers career opportunities and internships in many areas relating to SCL research. Check out the details at opportunities.

* These links will take you from the Intel Web site. Intel does not control the content on these Web sites.

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