Intel's 0.13 micron process features 0.06 micron gate length transistors and six layers of copper interconnect. Intel is breaking barriers to Moore's Law and has recently shown the world's smallest transistor, with a gate length of 15nm. Intel has also recently disclosed details of the TeraHertz transistor for building CPUs and all logic products in the second half of the decade. A key objective of the TeraHertz transistor is to allow the scaling predicted by Moore's Law while containing the exponential power problem that would otherwise make future chips impractical. The TeraHertz transistor contains new materials and new transistor structures that deliver BOTH high performance and low power. See the following documents for further information on the TeraHertz transistor.

"TeraHertz Transistor Backgrounder"
(Acrobat PDF file, 121KB)
Subject: A tutorial on the TeraHertz transistor and its benefits
Date: November 26, 2001

"New Transistors for 2005 and Beyond"
(Acrobat PDF file, 1867KB)
Subject: A basic guide to the TeraHertz transistor and its benefits
Date: November 26, 2001

"New Transistors for 2005 and Beyond"
(Acrobat PDF file, 2215KB)
Subject: Detailed information on the TeraHertz transistor and its benefits
Presenters: Gerald Marcyk, Robert Chau
Date: November 26, 2001

Intel recently opened the world's first 300mm wafer research laboratory. Named RP1 (RP stands for research and pathfinding), the $250 million facility is the first of its kind dedicated to research in advanced silicon process technologies on the new, larger 300mm wafers. Further information on this facility is available in the presentation dated May 11, 2001 below.

• "Breaking Barriers to Moore's Law"
  (Acrobat PDF file, 2,578 KB)
  Presenter: Gerald Marcyk
  Event: Intel Developer Forum
  Date: February 28, 2002
  
  
• "Enlightenment Beyond Classical CMOS"
  (Acrobat PDF file, 2,712 KB)
  Presenter: Paolo Gargini
  Event: 2002 Industry Strategy Symposium*
  Date: January 6-9, 2002
  
  
• "A 50nm Depleted-Substrate CMOS Transistor (DST)"
  (Acrobat PDF file, 1724 KB)
  Presenter: R. Chau
  Co-Authors: J. Kavalieros, B. Roberds, A. Murthy, B. Doyle, D. Barlage, M. Doczy and R. Arghavani
  Event: 2001 International Electron Devices Meeting*
  Date: December 5, 2001
  
  
• "High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics"
  (Acrobat PDF file, 1727 KB)
  Presenter: R. Chau
  Co-Authors: R. Arghavani, D. Barlage, G. Dewey, B. Doyle, M. Doczy, J. Kavalieros, A. Murthy, and B. Roberds
  Event: 2001 International Electron Devices Meeting*
  Date: December 4, 2001
  
  
• "An Enhanced 130 nm Generation Logic Technology Featuring 60 nm Transistors Optimized for High Performance and Low Power at 0.7 - 1.4 V "
  (Acrobat PDF file, 400 KB)
  Presenter: Scott Thompson
  Co-Authors: M. Alavi, R. Arghavani, A. Brand, R. Bigwood, J. Brandenburg, B. Crew, V. Dubin, M. Hussein, P. Jacob, C. Kenyon, E. Lee, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, M. Prince, R. Schweinfurth, S. Sivakumar, P. Smith, M. Stettler, S.Tyagi, M. Wei, J. Xu, S. Yang and M. Bohr
  Event: 2001 International Electron Devices Meeting^*
  Date: December 4, 2001
  
  
• "A General Partition Scheme for Gate Leakage Current Suitable for MOSFET Compact Models"
  (Acrobat PDF file, 71 KB)
  Presenter: Wei-Kai Shih
  Co-Authors: R. Rios, P. Packan, K. Mistry and T. Abbott
  Event: 2001 International Electron Devices Meeting^*
  Date: December 4, 2001
  
  
• "Silicon Technology: Scaling For the Second Half of the Decade"
  (Acrobat PDF file, 1,460 KB)
  Author: Gerald Marcyk
  Conference: Intel Developer Forum Fall 2001
  Date: August 28, 2001
  
  
• "Intel Technology and Product Leadership"
  (Acrobat PDF file, 2293 KB)
  Presenter: Paul Otellini
  Presented at the official press announcement
  "Intel Transforms Notebook PCs With New Mobile Pentium� III Processor-M"
  Date: July 30, 2001, Santa Clara, California
  
  
• "30nm and 20nm Physical Gate Length CMOS Transistors"
  (Acrobat PDF file, 1,086 KB)
  Presenters: Robert Chau
  Presented at the "2001 Silicon Nanoelectronics Workshop"
  Date: June 10-11, 2001, Kyoto, Japan
  
  
• "Intel Establishes New Transistor Performance Record"
  (Acrobat PDF file, 1,340 KB)
  Presenters: Robert Chau, Gerald Marcyk
  Date: June 10, 2001
  
  
• "Intel Research & Development RP1 Lab"
  (Acrobat PDF file, 6,680 KB)
  Presenter: Gerald Marcyk
  Date: May 11, 2001
  
  
• "Intel Process Technology Trends"
  (Acrobat PDF file, 7,836 KB)
  Presenter: Paolo Gargini
  Event: Intel Developer Forum, February 26, 2001
  
  
• "Intel Technology Briefing"
  (Acrobat PDF file, 435 KB)
  Presenters: Gerald Marcyk, Robert Chau
  Date: December 11, 2000
  
  
• "30nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays"
  (Acrobat PDF file, 204 KB)
  Authors: R. Chau, R. Arghavani, D. Barlage, G. Dewey, B. Doyle, M. Doczy, J. Kavalieros, D. Lionberger, A. Murthy, B. Roberds, R. Schenker
  Conference: IEEE International Electron Devices Meeting (IEDM), December 11, 2000
  
  
• "A 130 nm Generation Logic Technology Featuring 70 nm Transistors, Dual VT Transistors and 6 Layers of Cu Interconnects"
  (Acrobat PDF file, 545 KB)
  Authors: S. Tyagi, M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, W. Chen, B. Crew, M. Hussein, P. Jacob, C. Kenyon, C. Lo, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, S. Thompson, B. Tufts, J. Xu, S. Yang, M. Bohr
  Conference: IEEE International Electron Devices Meeting (IEDM*), December 11-13, 2000
  
  
• "Intel Technology and Manufacturing Group Update"
  (Acrobat PDF file, 3,235 KB)
  Presenter: Mike Splinter
  Conference: * Annual Technology Conference, November 28, 2000
  
  
• "Intel Technology Briefing"
  (Acrobat PDF file, 242 KB)
  Presenters: Sunlin Chou, Mark Bohr
  Event: 0.13 Micron Process Technology Announcement, November 7, 2000
  
  
• "Scalability Revisited: 100 nm PD-SOI Transistors and Implications for 50 nm Devices"
  (Acrobat PDF file, 272 KB)
  Authors: K. Mistry, T. Ghani, M. Armstrong, S. Tyagi, P. Packan, S. Thompson, S. Yu, M. Bohr
  Conference: 2000 IEEE Symposium on VLSI Technology, June 12-14, 2000
  
  
• "Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors"
  (Acrobat PDF file, 85 KB)
  Authors: T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, M. Bohr
  Conference: 2000 IEEE Symposium on VLSI Technology, June 12-14, 2000
  
  
• "100 nm Gate Length High Performance / Low Power CMOS Transistor Structure"
  (Acrobat PDF file, 112 KB)
  Authors: T. Ghani, S. Ahmed, P. Aminzadeh, J. Bielefeld, P. Charvat, C. Chu, M. Harper, P. Jacob, C. Jan, J. Kavalieros, C.Kenyon, R. Nagisetty, P. Packan, J. Sebastian, M.Taylor, J. Tsai, S. Tyagi, S. Yang, M. Bohr
  Conference: 1999 IEEE International Electron Devices Meeting (IEDM*), December 1999
  
  
  

• "A 50nm Depleted-Substrate CMOS Transistor (DST)"
  (Acrobat PDF file, 986 KB)
  Authors: R. Chau, J. Kavalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds and M. Doczy
  Event: 2001 International Electron Devices Meeting*
  Date: December 4, 2001
  
  
• "High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics"
  (Acrobat PDF file, 847 KB)
  Authors: D. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley and R. Chau
  Event: 2001 International Electron Devices Meeting*
  Date: December 4, 2001
  
  
• "An Enhanced 130 nm Generation Logic Technology Featuring 60 nm Transistors Optimized for High Performance and Low Power at 0.7 - 1.4 V"
  (Acrobat PDF file, 379 KB)
  Authors: S. Thompson, M. Alavi, R. Arghavani, A. Brand, R. Bigwood, J. Brandenburg, B. Crew, V. Dubin, M. Hussein, P. Jacob, C. Kenyon, E. Lee, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, M. Prince, R. Schweinfurth, S. Sivakumar, P. Smith, M. Stettler, S.Tyagi, M. Wei, J. Xu, S. Yang and M. Bohr
  Event: 2001 International Electron Devices Meeting^*
  Date: December 4, 2001
  
  
• "A General Partition Scheme for Gate Leakage Current Suitable for MOSFET Compact Models"
  (Acrobat PDF file, 69 KB)
  Authors: W.-K. Shih, R. Rios, P. Packan, K. Mistry and T. Abbott
  Event: 2001 International Electron Devices Meeting^*
  Date: December 4, 2001
  
  
• "Papers presented at the 2001 IEEE international Interconnect Technology Conference"
  (Acrobat PDF file,16 KB)
  Conference: 2001 IEEE international Interconnect Technology Conference, San Francisco , California
  Date: June 4-6, 2001
  
  
• "30nm and 20nm Physical Gate Length CMOS Transistors"
  (Acrobat PDF file, 917 KB)
  Author: Robert Chau
  Conference: Silicon Nanoelectronics Workshop, Kyoto, Japan
  Date: June 10, 2001
  
  
• "30nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays"
  (Acrobat PDF file, 112 KB)
  Authors: R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, G. Dewey
  Publication: Proceedings of IEEE International Electron Devices Meeting (IEDM*), December 11, 2000
  
  
• "A 130 nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 layers of Cu Interconnects"
  (Acrobat PDF file, 129 KB)
  Authors: S. Tyagi, M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, W. Chen, B. Crew, M. Hussein, P. Jacob, C. Kenyon, C. Lo, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, S. Thompson, B. Tufts, J. Xu, S. Yang, M. Bohr
  Publication: Proceedings of IEEE International Electron Devices Meeting (IEDM*), December 11, 2000
  
  
• "Scalability Revisited: 100 nm PD-SOI Transistors and Implications for 50 nm Devices"
  (Acrobat PDF file, 112 KB)
  Presenter: K. Mistry, T. Ghani, M. Armstrong, S. Tyagi, P. Packan, S. Thompson, S. Yu, M. Bohr
  Publication: Proceedings of the 2000 IEEE Symposium on VLSI Technology, June 12-14, 2000
  
  
• "Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors"
  (Acrobat PDF file, 135 KB)
  Authors: T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, M. Bohr
  Publication: Proceedings of the 2000 IEEE Symposium on VLSI Technology*, June 12-14, 2000
  
  
• "100 nm Gate Length High Performance / Low Power CMOS Transistor Structure"
  (Acrobat PDF file, 42 KB)
  Authors: T. Ghani, S. Ahmed, P. Aminzadeh, J. Bielefeld, P. Charvat, C. Chu, M. Harper, P. Jacob, C. Jan, J. Kavalieros, C. Kenyon, R. Nagisetty, P. Packan, J. Sebastian, M. Taylor, J. Tsai, S. Tyagi, S. Yang, M. Bohr
  Publication: Proceedings of 1999 IEEE International Electron Devices Meeting (IEDM*), December 1999