130nm Logic Technology Featuring 60nm Transistors, Low-K Dielectrics, and Cu Interconnects Scott Thompson Technology and Manufacturing Group, Intel Corporation
Mohsen Alavi Technology and Manufacturing Group, Intel Corporation
Makarem Hussein Technology and Manufacturing Group, Intel Corporation
Pauline Jacob Technology and Manufacturing Group, Intel Corporation
Chris Kenyon Technology and Manufacturing Group, Intel Corporation
Peter Moon Technology and Manufacturing Group, Intel Corporation
Matthew Prince Technology and Manufacturing Group, Intel Corporation
Sam Sivakumar Technology and Manufacturing Group, Intel Corporation
Sunit Tyagi, Jr. Technology and Manufacturing Group, Intel Corporation
Mark Bohr Technology and Manufacturing Group, Intel Corporation
Index Words: CMOS transistor, logic technology, copper interconnects
Citation for this paper: Thompson, S., Alavi, M., Hussein, M., Jacob, P., Kenyon, C., Moon, P., Prince, M., Sivakumar, S., Tyagi, S. and Bohr, M., "130nm Logic Technology Featuring 60nm Transistors, Low-K Dielectrics, and Cu Interconnects." Intel Technology Journal. http://developer.intel.com/technology/itj/2002/volume06issue02/ (May 2002).
ABSTRACT
Transistor gate dimensions have been reduced 200X during the past 30 years (from 10mm in the 1970s to a present-day size of 0.06mm). The transistor and feature size scaling have enabled microprocessor performance to increase exponentially with transistor density and microprocessor clock frequency doubling every two years. In this paper we describe Intel's latest 130nm CMOS logic technology used to make high-performance microprocessors >3GHz.
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