By Lin Chao
Publisher, Intel Technology Journal

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Since the invention of the integrated circuit some forty years ago, engineers and researchers around the world have worked on how to put more speed, performance and value onto smaller chips of silicon. By the end of this decade (2010) we at Intel want to reach the goal of 10 billion transistors on a single chip. This is a big challenge. Today we continue to break barriers to reach this goal. This issue (Q2, 2002, Vol. 6 Issue 2) of the Intel Technology Journal gives a detailed look into the exciting advances in the areas of transistor architecture, interconnects, dielectrics, lithography, and packaging.

This past year there have been many recent fundamental breakthroughs, particularly in five areas. Here we summarize some of those breakthroughs.

Manufacturing process: A new manufacturing process called 130 nanometer process technology (a nanometer is a billionth of a meter) allows Intel today to manufacture chips with circuitry so small it would take almost 1,000 of these "wires" placed side-by-side to equal the width of a human hair. This new 130-nanometer process has 60nm gate-length transistors and six layers of copper interconnect. This process is producing microprocessors today with millions of transistors and running at multi-gigahertz clock speeds.

Wafer size: Wafers, which are round polished disks made of silicon, provide the base on which chips are manufactured. Use a bigger wafer and you can reduce manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches) diameter silicon wafer size, up from the previous wafer size of 200mm (about 8 inches). 300 millimeter is the size of a medium pizza in the United States, up from the previous size of a small pizza!

Lithography: Lithography is the technology used to �print� intricate patterns that define circuits on silicon wafers. With our extreme ultraviolet (EUV) program, we've made a fundamental breakthrough in the area of lithography. EUV lithography is the technology that allows printing of lines smaller than 50nm. A few years ago, we realized that the light spectrums we were using were no longer scalable. We needed the shorter wavelengths of extreme ultraviolet beams. But rather than magnifying the beam through a glass lens as before, we now use mirrors. About five years ago we launched the industry consortium for EUV, and this year we demonstrated the first EUV using mirroring techniques.

Packaging: A silicon chip is useless without its package. The package delivers the power the chip needs and transfers all the information into and out of the chip. BBUL ("Bumpless Build-Up Layer") packaging is a new microprocessor packaging technology that has been developed by Intel. It is called bumpless because, unlike today's packages, it does not use tiny solder bumps to attach the silicon die to the package wires. Instead of having the die on top, the die is embedded in the package. It has build-up layers because the package is "grown" (built up) around the silicon die rather than being manufactured separately and bonded to it. This package is smaller, improves package inductance characteristics, and is better for multi-chip packaging.

The seven papers in this Q2, 2002, issue of Intel Technology Journal discuss the details on fundamental advancements of silicon process and manufacturing, including improvements in current technologies of 130nm logic technology, manufacturing using 300mm wafers, flash memory, digital CMOS integrated with analog RF signal elements, and next-generation advancement underway in lithography, transistor structure, and packaging technologies.